Date: Wed, 08 Jan 1997 21:43:59 GMT
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<h1>CSE467: Advanced Logic Design</h1>
<h3>Carl Ebeling, Spring 1996 </h3>

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<H3>Sample test fixtures</H3>
You may find these sample .tf Verilog test fixtures useful as examples during the quarter.  Each one includes a header describing its operation.<br>

<ul>
  <li><a HREF="example1.tf">EXAMPLE1.TF</a>
  <li><a HREF="example2.tf">EXAMPLE2.TF</a>
  <li><a HREF="example3.tf">EXAMPLE3.TF</a>
  <li><a HREF="example4.tf">EXAMPLE4.TF</a>
	<ul>
	<li><a HREF="infile">INFILE</a>
	</ul>
  <li><a HREF="example5.tf">EXAMPLE5.TF</a>
</ul>

<address>
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ebeling@cs.washington.edu
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